A recent trend of a thin flat panel is toward more and more increasing in size. In particular, in the field of television, there is a situation where even a liquid crystal panel exceeding 100 inches is put into the market, and it is thought that the trend will never change. However, along with the increase in size of a liquid crystal panel, a data line load of a TFT LCD (Thin Film Transistor Liquid Crystal Display) becomes increasingly large, and therefore power consumed in an amplifier of an LCD driver that drives the TFT LCD tends to increase. Further, in order to reduce the number of LCD drivers to be used, the number of outputs of one chip tends to increase more and more. That is, a power consumption amount by one chip increases more and more. As a result, the power consumption amount as a whole of LCD drivers increases, and thereby a chip temperature abnormally rises.
Among measure for the temperature rising of a chip, one having been recently focused on is a method that reduces power consumed by a chip. In this method, a voltage VDD/2 that is a half of a power supply voltage VDD is supplied to the chip, and an amplifier operates in the voltage VDD/2.
However, as this method becomes widespread, there arise various circuit-based problems. For example, there is a problem that, in the case of a conventional circuit, if only a differential stage is operated in the range of VSS (GND) to VDD, and an output stage is operated with the VDD/2 power supply, a voltage balance cannot be maintained on the circuit operation, and therefore a desired characteristic cannot be obtained.
In conjunction with the above, Patent literature 1 (JP 2002-175052A) discloses an operational amplifier. The operational amplifier is intended to reduce a power consumption amount. In the following, referring to FIGS. 1 to 3, the conventional operational amplifier in the Patent literature 1 will be described.
FIG. 1 is a circuit diagram showing a configuration of the conventional operational amplifier circuit in the Patent literature 1. The conventional operational amplifier circuit is provided with two differential type input stage circuits 140 and 240, two drive stage circuits 130 and 230, four switch circuits 30, 40, 50, and 60, two P-channel MOS transistors MP180 and MP280 and two N-channel MOS transistors MN180 and MN280. It should be noted that each of the two differential type input stage circuits 140 and 240 and two drive stage circuits 130 and 230 is supplied with a power supply voltage (VDD) and a power supply voltage (VSS).
The drive stage circuit 130 is connected to an output terminal 110 through drains of the P-channel MOS transistor MP180 and the N-channel MOS transistor MN180. Similarly, the drive stage circuit 230 is connected to an output terminal 210 through drains of the P-channel MOS transistor MP280 and the N-channel MOS transistor MN280. A source of the P-channel MOS transistor MP180 is supplied with the power supply voltage VDD. A source of the N-channel MOS transistor MN180 is supplied with a half (VDD/2) of the power supply voltage VDD. Also, a source of the P-channel MOS transistor MP280 is supplied with a half (VDD/2) of the power supply voltage VDD. A source of the N-channel MOS transistor MN280 is supplied with the power supply voltage VSS.
The switch circuit 30 is provided with switches SW301 to SW304, and controls connections between output terminals 110 and 210 and odd-numbered and even-numbered terminals 310 and 320. The switch circuit 40 is provided with switches SW401 to SW404, and controls connections between terminals 410 and 420 and input terminals 120 and 220 of the differential type input stage circuits 140 and 240. It should be noted that the terminal 410 is supplied with a voltage INP from a positive-side DAC (digital analog converter), and the terminal 420 is supplied with a voltage INN from a negative-side DAC. The switch circuit 50 is provided with four switches SW501 to SW504, and controls connections between the differential type input stage circuits 140 and 240 and the drive stage circuits 130 and 230. The switch circuit 60 is provided with four switches SW601 to SW604, and controls connections between the output terminals 110 and 210 and input terminals 121 and 221 of the differential type input stage circuits 140 and 240.
The conventional operational amplifier circuit can use the switch circuits 30 to 60 to change a configuration of an amplifier circuit that drives the odd-numbered and even-numbered terminals 310 and 320. Specifically, in a pattern 1, the eight switches SW301, SW303, SW401, SW403, SW501, SW503, SW601, and SW603 are in an ON state, and the eight switches SW302, SW304, SW402, SW404, SW502, SW504, SW602, and SW604 are in an OFF state, and the pattern 1 and a pattern 2 opposite to the pattern 1 are switched to each other.
In the case of the pattern 1, the voltage INP is supplied from the positive-side DAC to an amplifier circuit including the differential type input stage circuit 140 and the drive stage circuit 130. Also, an output is outputted from the output terminal 110 to the odd-numbered terminal 310 as an odd-numbered output Vodd. At this time, the voltage INN is supplied from the negative-side DAC to an amplifier circuit including the differential type input stage circuit 240 and the drive stage circuit 230. Also, an output is outputted from the output terminal 210 to the even-numbered terminal 320 as an even-numbered output Veven.
On the other hand, in the case of the pattern 2, the voltage INP is supplied from the positive-side DAC to an amplifier circuit including the differential type input stage circuit 240 and the drive stage circuit 130. Also, an output is outputted from the output terminal 110 to the even-numbered terminal 320 as the even-numbered output Veven. At this time, the voltage INN is supplied from the negative-side DAC to an amplifier circuit including the differential type input stage circuit 140 and the drive stage circuit 230. Also, an output is outputted from the output terminal 210 to the odd-numbered terminal 310 as the odd-numbered output Vodd.
The conventional operational amplifier circuit operates as follows, to drive capacitive loads connected to the odd-numbered and even-numbered terminals 310 and 320. At this time, the differential type input stage circuits 140 and 240 and the drive stage circuits 130 and 230 operate in a voltage range of the positive power supply voltage VDD to the negative power supply voltage VSS. Also, the MOS transistors MP180 and MN180 and the MOS transistors MP280 and MN280 are output transistors, and respectively operate in voltage ranges of VDD to VDD/2 and VDD/2 to VSS. This results in the power consumption amount consumed in an output stage to be approximately halved.
FIG. 2 is a circuit showing a configuration of the differential type input stage circuit 140 shown in Patent literature 1. The differential type input stage circuit 140 is provided with six P-channel MOS transistors MP101, MP102, MP103, MP104, MP105, and MP106, and four N-channel MOS transistors MN101, MN102, MN103, and MN104. It should be noted that sources of the four P-channel MOS transistors MP103, MP104, MP105, and MP106 are connected with the positive power supply voltage VDD. Sources of the two N-channel MOS transistors MN103 and MN104 are connected with the negative power supply voltage VSS. Sources of the two N-channel MOS transistors MN101 and MN102 are connected to the power supply voltage VSS through a constant current source I101. Sources of the two P-channel MOS transistors MP101 and MP102 are connected to the power supply voltage VDD through a constant current source I102.
The two P-channel MOS transistors MP101 and MP102 constitutes a differential pair. The two N-channel MOS transistors MN103 and MN104 constitute an active load for the differential pair.
Also, the two N-channel MOS transistors MN101 and MN102 constitutes a differential pair. The two P-channel MOS transistors MP103 and MP104 and the two P-channel MOS transistors MP105 and MP106 respectively constitute current mirror circuits. Outputs of the current mirror circuits are connected to drains of the two N-channel MOS transistors MN103 and MN104.
Further, the input terminal 120 is connected to respective gates of the N-channel MOS transistor MN101 and the P-channel MOS transistor MP102. The input terminal 121 is connected to respective gates of the N-channel MOS transistor MN102 and the P-channel MOS transistor MP101.
Also, respective drains of the N-channel MOS transistor MN104 and the P-channel MOS transistor MP106 are connected to the two switches SW501 and SW502 through a terminal 123.
Based on such a configuration, differential input signals supplied to the input terminals 120 and 121 are subjected to conversion, and then outputted from the terminal 123.
A configuration and an operation of the differential type input circuit 240 are the same as those described above. However, it should be noted that the two input terminals 120 and 121, a terminal 123, and two switches SW501 and SW502 should be replaced by the two input terminals 220 and 221, a terminal 223, and switches SW503 and SW504, respectively.
FIG. 3 is a circuit showing a configuration of the conventional drive stage circuit 130. The drive stage circuit 130 is provided with three P-channel MOS transistors MP107 to MP109, an N-channel MOS transistor MN105, a P-channel MOS transistor MP110, and two constant current sources 103 and 104. It should be noted that a source of each of the three P-channel MOS transistors MP107 to MP109 is supplied with the power supply voltage VDD. A source of the N-channel MOS transistor MN105 is supplied with the power supply voltage VSS. Each of the two constant current sources 103 and 104 is supplied with the power supply voltage VSS.
A gate of the N-channel MOS transistor MN105 is connected to the two switches SW501 and SW502 through a terminal 131. A drain of the N-channel MOS transistor MN105 is connected to a drain of the P-channel MOS transistor MP107.
The P-channel MOS transistor MP107 constitutes a current mirror circuit with each of the P-channel MOS transistors MP108 and MP109. A drain of the P-channel MOS transistor MP108 is connected to the constant current source 103 through the P-channel MOS transistor MP110. A gate of the P-channel MOS transistor MP110 is connected to a gate of the P-channel MOS transistor MP180. A drain of the P-channel MOS transistor MP109 is connected to a gate of the N-channel MOS transistor MN180 and the constant current source 104.
According to such a configuration, in the drive stage circuit 130, an input voltage supplied from the terminal 131 is received by the N-channel MOS transistor MN105, of which output drives the P-channel MOS transistor MP180 and the N-channel MOS transistor MN180. That is, a composite output signal according to an input signal from the terminal 131 is outputted from the terminal 110.
The drive stage circuit 230 also has the same configuration and operation. However, it should be noted that the P-channel MOS transistor MP280, the N-channel MOS transistor MN280, the terminal 132, and two switches SW501 and SW503 should be replaced by the P-channel MOS transistor MP280, the N-channel MOS transistor MN280, the terminal 231, and two switches SW502 and SW504, respectively.